The present invention relates to a time-to-digital converters for converting signal phase differences to digital values.
In recent years, as digital phase locked loop circuits develop, time-to-digital converters, which digitize analog temporal information, have been actively developed. A typical time-to-digital converter receives a first signal into an inverter chain having a plurality of inverter circuits coupled in series, latches the output of each inverter circuit in synchronism with a second signal, and detects the point at which the status of the inverter chain changes, thereby digitizing the phase difference or time difference between the first and the second signals.
However, the numbers of latch circuits and comparators which the time-to-digital converter has to have in order to generate an n-bit digital code are each nth power of 2, which is disadvantageous in terms of circuit scale and power consumption. Thus, successive approximation time-to-digital converters for performing time-to-digital conversion by a binary search have been proposed.
In general, a successive approximation time-to-digital converter includes a plurality of time-to-digital conversion circuits coupled in cascade. In each time-to-digital conversion circuit, a phase comparator compares phases of two input signals with each other to generate a 1-bit digital value, and based on a result of the comparison of the phases, a route switch switches between routes of the two input signals such that one of the input signals which has a leading phase is input via a delay unit to a time-to-digital conversion circuit in a subsequent stage, and the other of the input signals which has a lagging phase is input directly to the time-to-digital conversion circuit in the subsequent stage. The delay units in the time-to-digital conversion circuits in the stages are set such that the delay time in each stage is reduced to a half of the delay time in a directly preceding one of the stages sequentially from the first stage, so that a time difference between the two signals input to the time-to-digital conversion circuit in the first stage is sequentially converted to a digital value by a binary search (see, e.g., Jinn-Shyan Wang, et. al, “An Ultra-Low-Power Fast-Lock-in Small-Jitter All-Digital DLL,” ISSCC 2005/SESSION 22/PLL, DLL, AND VCOs/22.7, Feb. 9, 2005, pp. 422-423,607).
In such a conventional time-to-digital conversion circuit, in order to prevent the two input signals from passing through the time-to-digital conversion circuit before determination of the result of the comparison of the phases, a delay unit has to be inserted in each of two input signal paths so as to delay input of the signals to the route switch. This increases not only latency, but also the circuit scale as well as power consumption of the time-to-digital conversion circuits and the time-to-digital converter including the time-to-digital conversion circuits coupled in cascade.
Thus, there are demands for a time-to-digital conversion circuit in which the latency, the circuit scale, and the power consumption are reduced.